In designing of recent large-scaled semiconductor integrated circuits (LSI), a so-called “variation problem” has become prominent, where characteristics of manufactured LSIs deviate from desired characteristics due to the influence of variations and the like of characteristics of transistors which make up the LSIs. As countermeasures to the variation problem, in the designing of an LSI, a number of proposals have been made for the provision of a circuit which includes a correction technique which can correct for deviations from desired values with external control signals after designing and manufacturing. A circuit for such a correction for variations has been widely employed in analog circuits, delay circuits and the like which are largely affected by variations Further, digital signals have been often employed for the external control signals, making it possible to more readily correct for variations.
However, as the variation problem becomes prominent and the design of LSI itself becomes complicated, a large amount of external control signals are required for variation corrections in increasingly more cases. In this event, the external control signals are applied to an LSI chip through control input terminals from the outside of the LSI chip, but due to limitations to the number of I/O (input/output) terminals in an LSI chip, it is increasingly more difficult to directly apply every external control signal individually to the LSI chip from the outside.
Accordingly, in semiconductor integrated circuits, a circuit as shown in FIG. 1, referred to as a serial input circuit, has been widely employed in general as a control signal input circuit such that a large amount of control signals can be applied through a limited number of input terminals. This serial input circuit, though comprising only two input terminals, is a circuit which is capable of outputting N items of control signals. The serial input circuit comprises M pieces of flip-flops FF1 to FFM connected in cascade, i.e., is configured to connect the output of a flip-flop at the previous stage to the input of a flip-flop at the following stage. Here, the two input terminals are an input terminal applied with signal DS, and a clock input terminal applied with clock signal CLKS. The outputs of the flip-flops connected in cascade are labeled DIN[1], DIN[2], . . . , DIN[M], respectively.
It is configured that the clock terminal of each flip-flop is commonly supplied with clock signal CLKS. When this serial input circuit is employed, first, desired M pieces of bit signals D11 to D1M are arranged in the order of D1M, . . . , D12, D11 in time series to form a serial signal in an input device provided externally to an integrated circuit, and the head of this bit sequence, DIM, is applied to the serial input circuit as signal DS. In other words, DIM is supplied to the input terminal of flip-flop F1 at the first stage. By applying a pulse once as clock signal CLKS, signal DS shifts one bit within the serial input circuit. Next, signal DS is switched to the second bit of the bit sequence within the external input device, and the pulse is applied once to clock input terminal CLKS. By repeating such operations M times, the desired M-bit signal appears at the outputs of M pieces of flip-flops FF1 to FFM in parallel, such as bit D11 appears at output DIN[1], bit D12 appears at output DIN[2], and so on.
The serial input circuits can be mutually connected in cascade at in any number of stages. For example, as shown in FIG. 2, for applying control signals 101 to 10N to N pieces of controlled circuits 201 to 20N, respectively, N pieces of the aforementioned serial input circuits for M bits may be connected in cascade, and among adjacent serial input circuits, DIN[M] at the last stage of a serial input circuit on the previous stage side may be connected to an input portion of signal DS of the serial input circuit on the following stage side. Control signals 101 to 10N are control signals each having a plurality of bits. By configuring such a multi-stage cascade connection, a total number of control signals is increased, and even if the number of controlled circuits (i.e., circuits under control) is increased, control signals can be applied through a small number of input terminals.
However, as a problem in the employment of such a serial input circuit, N×M pieces of flip-flops are required as data holding circuits in order to apply N×M items of control signals, so that when a large number of external control signals must be applied, the serial input circuit occupies a large area within a semiconductor integrated circuit. Also, even when part of a large number of external control signals is to be changed, a serial signal of N×M bits must be generated again, and the generated signals must be applied again to all the flip-flops within the serial input circuit. In this event, problems arise in that a time overhead occurs because the serial signal is applied again, an external input device is required for storing a serial signal of N×M-bits and generating again the serial signal of N×M-bits from all control signals when the control signal is changed, and a control algorithm becomes complicated.
As techniques related to the present invention, Japanese Patent Laid-open Application No. 2002-41356 (JP-A-2002-041356) discloses a semiconductor device which contains a controlled circuit, where a control signal can be supplied to the controlled circuit at high speeds. Japanese Patent Laid-open Application No. 2003-108516 (JP-A-2003-108516) discloses a high-speed bus interface for use in a semiconductor testing apparatus, where the number of bus signal lines can be reduced, and the order of signal lines can be arbitrarily set. In this bus interface, s serial/parallel conversion circuit is provided between an interface unit to an internal circuit and an input stage. Japanese Patent Laid-open Application No. SHO-61-99993 (JP-A-61-099993) discloses a latch circuit which delivers input data as it is when a trigger signal is at a first level, and holds previously delivered output data when the trigger signal is at a second level different from the first level. Japanese Patent Laid-open Application No. Hei-8-314410 (JP-A-8-314410) discloses an enable circuit for use in a driving circuit of a liquid crystal display device, where the enable circuit delivers input data as it is when an enable signal is at a first level, and the level of the output goes to a second level when the enable signal is at the second level. Japanese Patent Laid-open Application No. Hei-9-152470 (JP-A-9-152470) discloses a circuit for use in an integrated circuit testing apparatus and for converting a high-speed serial signal to a low-speed parallel signal. Japanese Patent Laid-open Application No. Hei-10-222418 (JP-A-10-222418) discloses a configuration which can make a write time to a non-volatile memory provided within a microprocessor equal to a machine cycle of the microprocessor.
The documents cited in this specification are enumerated below:                Patent Literature 1: JP-A-2002-041356,        Patent Literature 2: JP-A-2003-108516,        Patent Literature 3: JP-A-61-099993,        Patent Literature 4: JP-A-8-314410,        Patent Literature 5: JP-A-9-152470,        Patent Literature 6: JP-A-10-222418.        